1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
It has been conventionally performed to feed a predetermined potential to a well, in order to prevent the potential of a well region from going into a floating state to cause a malfunction in a semiconductor device. FIG. 10 of US2004/125676 A1 and US2006/028853 A1 show a structure in which a p-type well layer is provided in a surface of a silicon substrate and a plurality of elements are disposed within an active region defined in the well layer by a trench isolation of an STI structure. In addition, US2004/125676 A1 and US2006/028853 A1 show a structure in which a high-concentration diffusion layer having the same polarity (p type) as the well layer is provided separately from the active region for element and power is fed from this diffusion layer to the well layer. In US2004/125676 A1 and US2006/028853 A1, the potential of the p-type well layer where respective elements are disposed is fixed by such a power feeding mechanism to the well.